High-speed analog-to-digital converters (ADCs) often use a capacitive DAC to generate a voltage residue after a coarse conversion that is further quantized to increase the overall conversion resolution. The accuracy for this residue generation is imposed by the required overall accuracy of the total ADC. For example, the DAC used in the first stage of a 14-bit linear ADC pipelined SAR ADC may require more than 14 bit linearity, although its own resolution can be limited to only a few bits. FIG. 1 shows an example of a 6-bit capacitive DAC with an input voltage Vin sampled on the top plate before the DAC is switched via the bottom plates of the capacitors to generate the output voltage Vout.
In general, the output voltage of a DAC as in FIG. 1 above with a resolution of N bits is Vout=Vin−Vdac withVdac=Voffset+Σk=0N-1bkVref  (1)wherein Vref denotes a reference voltage and Voffset a fixed offset voltage independent of the input voltage Vin. The coefficients bk correspond to a coarse digitalization of the input voltage Vin.
The non-linearity arises from a mismatch on the coefficients bk which may be binary scaled, and from the variation of the reference voltage Vref with the input code bN-1 . . . b0. In a capacitive DAC the coefficients are determined by ratios of capacitors. Hence, capacitor mismatch introduces linearity errors. Various techniques exist to compensate for these errors, like calibration, digital compensation or just increasing the area or size of the capacitors to decrease the mismatch.
When a capacitive DAC switches, it draws some charge from the reference node. This amount of charge depends on the code applied at the input of DAC. With an ideal voltage source at the reference, this code-dependent charge does not change the voltage Vref on the reference node. In reality, however, the reference node is either driven by an on-chip buffer or it is connected to an external pin. With an on-chip buffer the voltage on the reference node drops each time the DAC switches and it takes some time to settle to the target reference voltage as shown in FIG. 2. A buffer with a small output impedance may be used. The drop depends on the DAC input code bN-1 . . . b0. The settling time is determined by an RC time constant with R the buffer output impedance and C a fraction of the DAC capacitance. To make the DAC linear, one has to wait until the voltage on the reference node is settled close enough to the target reference voltage. This puts a limitation on the speed that can be obtained with the DAC.
When the reference node is connected to an external pin, the inductance of the bond wire causes code-dependent ringing on the reference node each time the DAC switches, as shown in FIG. 3. Again, extra delay may be added before the DAC output can be used with the correct reference voltage. Alternatively, a large decoupling capacitor can be put on-chip which may occupy a significant amount of chip area.
It has been proposed in the art to stabilize the reference by adding a capacitive network on the reference node as shown in FIG. 4. The fixed capacitor Cref is pre-charged to the nominal reference voltage Vref and a variable capacitor Caux to a pre-charge voltage Vaux. This voltage Vaux can be any voltage different from Vref but for practical reasons the most straightforward choice is the electrical ground (zero). For a certain DAC configuration and a certain DAC switching event, the charge for the DAC can be computed as well as the value of Caux to make the total charge drawn from Cref independent of the selected DAC code. To achieve this code-independent Qref, the correct mapping of DAC code onto setting for Caux should be implemented as indicated in FIG. 4.
The proposed scheme, however, also poses some limitations on the ADC in terms of speed and accuracy. After the DAC has switched and the residue has been processed, the DAC may go back to the initial situation to be ready for the new sample. This DAC resetting also draws a code-dependent charge from the reference capacitor Cref An example for a 6-bit capacitive DAC is shown in FIG. 5. It shows the voltage on the DAC reference node after switching the DAC to generate the residue (squares) including the Caux, and after resetting the DAC back to its initial state (dots). To ensure Cref is pre-charged back to Vref with sufficient accuracy over all codes, it needs enough time to settle during the pre-charging phase which results in a speed penalty.
An optimized value for Caux depends on the DAC characteristics as well as on the reference capacitance Cref and the external voltages Vref and Vaux. Due to process variations it is difficult to estimate them with high accuracy and, hence, to know a DAC code mapping onto a setting for Caux. Furthermore, changes in the external reference voltages are not accounted for at all.
When the DAC is used in a traditional SAR algorithm, it switches N times and draws N times charge from Cref Consequently, the compensation with Caux takes N times the time to find the correct value for Caux and switch it. Retrieving the correct value for Caux is usually also time-consuming especially when it requires access to a memory. One way to reduce this problem is to use the Caux only in the first few steps of the algorithm.
Time-interleaving is typically employed to increase the total conversion speed of ADCs. The scheme presented in FIG. 4, however, may include a tunable capacitor Caux for each channel. For large interleaving factors, this results in an increase of the occupied area.
In a time-interleaved ADC with multiple channels, a different final reference voltage per channel—albeit independent over the codes within a channel—results in gain mismatches between the channels as can be derived from equation (1). These mismatches introduce spurs which limit the overall accuracy. In order to compensate for these gain mismatches, digital correction can be considered but that comes at the cost of a considerably increased complexity.
Hence, there is room for improvement, so that at least one or more of these drawbacks of alternative schemes may be solved or avoided.